Jianping Zeng

Tenure-track Assistant Professor School of Computing and Augmented Intelligence (SCAI)
Arizona State University 660 S. Mill Avenue Tempe, AZ 85281, USA
Office: CTRPT 203-05 Google Scholar DBLP
jpzeng (at) asu (dot) edu

Biography

I am a Tenure-track Assistant Professor in the School of Computing and Augmented Intelligence (SCAI) at ASU since Fall 2025. Before that, I was a computer architecture researcher in the Samsung Memory Solutions Lab (MSL) with a Ph.D. degree in Computer Science from Purdue University under the guidance of Prof. Changhee Jung. Prior to joining Purdue University, I worked as a compiler engineer with focus on optimizing GCC and Clang/LLVM compilers at Alibaba Group, China.



I will take on 1-2 PhD students to start in Fall 2026, focusing on hardware/software co-design for performance, reliability, and security issues. Please email me your CV, transcript, and English test report, if you are interested in working with me.


Research

At ASU, I lead the Phoenix Architecture and Compiler Exploration (PACE) Lab, focusing on compilers and computer architectures. Specifically, PACE lab aims to co-design compilers and computer architectures, driven by application-level demand, addressing performance, reliability, and security issues of computing systems including energy harvesting systems and data centers. My prior research work is typically published at top-tier venues in computer architecture, high-performance computing, and programming languages, e.g., ISCA, MICRO, ICS, and PLDI.

PACE Lab Figure

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